Tutor: RECH IVAN Major Research topic
:A STUDY OF HIGH-PERFOMANCE FREQUENCY SYNTHERSIZER FOR WIRELESS APPLICATIONS IN NANOMETER CMOS TECHNOLOGIES
Advisor: LEVANTINO SALVATOREAbstract:
High-performance frequency synthesizer is a fundamental part of almost any modern wireless communication device, for example, used for coherent demodulation/modulation in wireless transceivers. The frequency synthesizer based on phase-locked loop (PLL) architecture is a negative feedback control system generating an output signal whose frequency is multiple of the reference signal frequency. The multiple can be an integer or a fractional number. Though fractional-N PLLs entail the key advantage of a finer frequency resolution, the noise-power figure-of-merit (FoM) of state-of-the-art integer-N PLLs is still better than in the fractional-N case. In addition, digital PLL synthesizers are taking over conventional analog ones, because of their benefits in terms of power consumption and area occupation in ultra-scaled CMOS technologies. In this project, we replaced the conventional multi-bit TDC with a one-bit time/digital converter (TDC) in a fractional-N second-order digital PLL, to reduce power-consumption and fractional spurs caused by the TDC. In this way, we aim to decrease the gap of FoM between fractional-N synthesizers and the best integer-N ones. However, the one-bit TDC (also known as bang-bang phase detector, BBPD), when employed in frequency synthesizers, has a linearized gain whose value is inversely proportional to power of the BBPD input phase error. Therefore, in the fractional-N PLL, large phase error induced from the accumulated quantization noise of the Delta-Sigma modulator (DSM) which drives the modulus of the divider may reduce the BBPD gain. As a result, it also reduces the loop bandwidth (BW) of the PLL and hence makes the PLL’s output phase noise becomes much larger since the digitally-controlled oscillator (DCO) noise is dominant in frequency synthesizers. To address this issue, we have introduced a controllable delay block, or in other words a digital/time converter (DTC), in the feedback path between the divider and the BBPD. Phase error from the DSM is cancelled out by the DTC so the DTC’s total range is exponentially dependent on the order of the DSM. Besides that, to calibrate the gain mismatch between the DCO period and the DTC resolution, an adaptive filter is implemented based on the least-mean-square (LMS) algorithm. The LMS coefficient is regulated by taking the covariance of the BBPD's output and the accumulated quantization error of the DSM. Depending on the linear characteristic of the DTC, LMS coefficient can be single (linear DTC) or multiple (non-linear DTC). Though via simulation it is known that a high-order DSM is needed to guarantee the LMS coefficient convergence time when the fractional part of the frequency control word (fcw) is a near integer constant input, the theory behind is still not well understood. In previous prototypes, a second-order DSM was used and hence the DTC range was at least two times of the DCO period (not including margin for mismatch). In the present study, firstly I have been concentrating on the theory related to the LMS coefficient convergence time, in particular for the case of single LMS gain. Then I have proposed a novel scheme that uses the first-order DSM driving the divider to reduce the required DTC range while keeping the LMS convergence time remains within the allowed range. Details of the study is explained as follows.
The expected value of the convolution of the BBPD output and the DSM accumulated quantization error is zero when the LMS loop is in the steady state. However, before reaching this state the BBPD output has to show a cross-correlation to the DSM accumulated quantization error. Otherwise, the LMS coefficient may not be updated to obtain the final value. It follows that, if we take the BBPD output signal during the transient process, its power spectrum shape in the frequency domain should be similar to the one of the DSM accumulated quantization error. Unfortunately, based on calculation as well as confirmed by simulation, we have understood that the transfer function of the BBPD's output signal versus the overall input-referred noise (including noise from the LMS loop) of the PLL attenuates low frequencies. The cut-off frequency of this transfer function is exactly the PLL loop BW. Consequently, when the first-order DSM is used and the fractional part of the fcw is close to integer number enough so most of the power of the induced accumulated quantization error locates at frequencies below the PLL BW, the cross-correlation becomes negligible. Therefore, the LMS coefficient needs a long time to converge or even unable to converge in this case. On the contrary, when a high-order DSM is used, because the power of the accumulated quantization error is shaped to higher frequencies above the PLL BW so the cross-correlation is not affected. This theory based result explains the simulation results related to the LMS coefficient convergence time obtained in the previous studies. It also implies that the convergence time of the LMS coefficient at the near integer channel can be improved by reducing the BW of the PLL. However, being the PLL BW is determined by the proportional path’s gain of the low-pass filter and the BBPD linearized gain, reducing the BW also means that it needs to decrease the proportional path’s gain or increase the noise level of the input-referred noise. It is obvious that these both methods are not suitable since they lead to a slow frequency-lock as well as an increased output jitter. Then, the analysis result shows that noise shaping is the only way to have a fast convergence time for all fractional part patterns of the fcw.
According to the analysis, I have proposed a novel scheme for the DTC control circuit. The basic idea of the proposed scheme is to put a dithering block with a shaped noise to dither the constant fcw before feeding it to the DSM driving the divider. For more details, the dithering block used here is a high-order digital DSM. In this topology, the fcw after passing through the dithering block will include an additional noise component varying with high speed. Since the dithering noise component has power being concentrated in the high frequencies regardless the fractional part of the original fcw its cross-correlation with the BBPD output is not attenuated in the LMS coefficient’s transient process. Thus, the proposed scheme allows using the first-order DSM to drive the divider without worrying about the LMS coefficient convergence time. On the other hand, when we introduce a new block in the circuit its induced noise into the PLL also needs to be cancelled out by the DTC. Here unlike the previous schemes require a large DTC range because of using the second-order DSM to drive directly the divider, the DTC range required for cancelling dithering noise in this case is much smaller because we can manage the noise amount. To do this, instead of dithering the entire fractional part of the fcw only one portion is passed by the dithering block by multiplying the fcw with a multi-factor. It will be the same as left shift of some fractional bits to integer bits if the multi-factor is a power of two. Then, to get back the modulus of the divider the output of the dithering block is divided by the same multi-factor. However, thanks to this technique the induced noise from the dithering block is inversely proportional to the multi-factor. The multi-factor is optimized so that the power of the dithering noise is large enough to be not affected by other noise sources in the PLL. As a result, the LMS coefficient can converge within the allowed time with the first-order DSM.
In parallel with the analyzing work, I am also designing a novel DTC for the next prototype PLL targeting a lower power consumption than the previous one while achieving the same level output jitter. The basic concept of this DTC is proposed from another group which relied on cascading multi buffer stages using full CMOS topology and hence the DTC consumes only dynamic power. In comparison with the current mode logic (CML) type this type consumes less power. However, in the presented scheme there is a pMOS transistor used as a switch in every stage which can be removed without affecting the circuit operation. By removing this transistor, size of the main transistors can be reduced since their load becomes lighter, subsequently, the circuit consumes less power. Moreover, the conventional circuit uses an inverter stage to create an additional inverted reference signal to reset all transistors to the default state in the second-half period. Because the inverted signal goes to all stages of the DTC, the inverter is composed of large size transistors which leads to a high-power consumption. To overcome this problem, I have proposed to use a signal having a similar behavior with the inverted reference signal. This signal is generated automatically in every delay stage and only drives one next stage so it does not need to be activated for all control codes. As a result, the average power consumption of the entire DTC is saved.
In the next step, I would like to summary the analysis so far into a paper to submit to a journal. Then, if it is possible I would like to extend the analysis for the case of multi LMS coefficients. Furthermore, it is also needed to evaluate the new DTC with experiments.