High-performance frequency synthesizer based on the nanometer CMOS technology is a fundamental part of almost any modern wireless communication device, for example, used for coherent demodulation/modulation in wireless transceivers. The frequency synthesizer based on phase-locked loop (PLL) architecture is a negative feedback control system generating an output signal whose frequency is multiple of the reference signal frequency. The multiple can be an integer or a fractional number. Though fractional-N PLLs entail the key advantage of a finer frequency resolution, the noise-power figure-of-merit (FoM) of state-of-the-art integer-N PLLs is still better than in the fractional-N case. In addition, digital PLL synthesizers are taking over conventional analog ones, because of their benefits in terms of power consumption and area occupation in ultra-scaled CMOS technologies. In this study, we replaced the conventional multi-bit phase detector (PD), which is indeed a time/digital converter (TDC), with a one-bit phase detector in a fractional-N second-order digital PLL, to reduce power-consumption and fractional spurious tones (spurs) caused by the TDC. Moreover, the linearized gain of the one-bit PD is inversely proportional to its input-referred noise variance while the one of the multi-bit PD is inversely proportional to its time resolution. Thus, the one-bit PD may obtain a larger gain which results a low output phase noise. In this way, we aim to decrease the gap of FoM between fractional-N synthesizers and the best integer-N ones.
However, the one-bit (also known as bang-bang, BB) phase detector, when employed in frequency synthesizer, acts like a non-linear hard limiter if the phase error at the PD input does not behave like a random noise. In that case, it may cause a limit cycle in the PLL, which gives rise to large spurs in the output phase noise spectrum. By analyzing, it is known that the dominant deterministic noise in the feedback path of the PLL are induced by the quantization noise of the DS modulators (DSM) driving the digitally-controlled oscillator (DCO) and the modulus control of the frequency divider. To address these quantization noise, we introduced a controllable delay block, or in other words a digital/time converter (DTC), in the feedback path between the integer divider and the BBPD. The DTC produces an out of phase signal with the quantization noise induced by the DSMs. The control gain of the DTC is automatically adjusted in background based on the least-mean-square (LMS) algorithm to adapt changes in the DCO frequency as well as the DTC characteristics in practice. Thanks to this structure, the PD input phase noise is reduced to the level of the random noise caused by unavoidable thermal sources in the PLL. Consequently, the BBPD operates as a linear element in steady-state (the state when the thermal noise is dominant at the PD input).
Beside the above-mentioned issue, the adoption of the BBPD in the PLL also follows one problem related to the locking time. In a typical BB digital PLL, the digital filter placed on the feedforward path between the PD and the DCO is consisted of a proportional path and an integral path. Gain of the proportional path decides the lock-range of the frequency while gain of the integral path decides the amount of increase (decrease) of the DCO period in every sampling cycle. In general, to guarantee the stability of the circuit, the integral path gain is much smaller than the proportional path gain. In addition, for high performance PLLs, a DCO with fine resolution (in order of kHz) is required. Obviously, the amount of change in the DCO frequency in every sampling clock is very small since the BBPD has only two output values, which are +1 and –1. As a result, it takes an extremely long transient or the PLL even fails to lock when a wide frequency step (in order of hundred MHz) is needed. To overcome this problem, a frequency-aid technique is proposed, essentially based on an added digital ternary phase detector (TPD) and a multi-bank DCO. This TPD is only activated when the time error between the reference signal and the feedback signal is over a fixed amount, which is called dead zone of the TPD. For the DCO, the coarse bank has a much bigger frequency resolution than the one of the fine bank. To shorten the locking time, the output of the TPD is fed to an integral path to directly generate tuning word for the DCO coarse bank. At the same time, another proportional path is created, however, with the output is added to the frequency control word. Therefore, the amount of change of the DCO frequency in one sampling clock can become bigger and the time error between the reference signal and the feedback signal is limited to prevent the PLL failing to lock.
In this study, we have analyzed for the first time the operation of the DTC control gain calibration loop and the frequency aid loop. Because during the transient process, the PD input time error is not dominated by the thermal random noise, the PD cannot be considered as a linear element. Therefore, analysis in frequency domain based on linearized model is not acceptable. Firstly, this study shows the dependence of the DTC time range on the order of the DSM driving the frequency divider. Then, the analysis explains the trade-off between the DTC time range and the convergence speed of the control gain which is relied on the LMS algorithm. Moreover, we have proposed two novel architectures for the DTC control loop to relax this trade-off. For the frequency aid loop, by a similar analysis in time domain, we have calculated the condition for the dead zone to avoid the limit cycle phenomenon as well as the maximum lockable frequency range in the circuit. We proposed the optimized value of the dead zone for fast frequency locking time as well. Some of the studied results have been published at conferences while others are submitted to the transaction paper and under review.