|MALAVENA GERARDO||Cycle: XXXIII |
Tutor: SOTTOCORNOLA SPINELLI ALESSANDRO
Advisor: MONZIO COMPAGNONI CHRISTIAN Major Research topic
:Investigation and modeling of Flash technologies: evolution towards 3-D architectures and applications to neuromorphic computingAbstract:
Since their first introduction, Flash memory technologies have been the object of an uninterrupted scaling process that allowed to increase their bit-storage density and become the most successful solution in the non-volatile memory market. However, shrinking the single cell size up to decananometer dimensions has faced some fundamental issues related not only to the manufacturing process itself, but also to inherent limitations of the physical mechanisms involved in the device operation that have undermined the memory array reliability. In this regard, as they target distinct applications, NAND and NOR Flash technologies have been following different scaling paths over the years.
In particular, as NAND Flash technology aims to provide a low cost solution to store a large amount of data, high integration density and operating data throughput are undeniable features to pursue during the technology development. For this reason, the improvement of NAND Flash memory arrays has been the real driving force behind the efforts devoted to push the technology scaling to its physical limits, and NAND Flash memory cells have reached the smallest feasible feature size equal to 14 nm in the middle of 2010’s decade. From then on, the conventional scaling approach has been replaced by an equivalent one, consisting in stacking many memory cells in the direction perpendicular to the plane of the wafer, thus breaking the trade-off between the dimension of each memory cell and the storage density. Although the resulting three-dimensional (3-D) NAND Flash memories determined a general improvement in terms of reliability, some new issues have emerged due their novel architecture. One of them is absence of a body contact, preventing to directly access the string channel to raise its potential during the erase operation, similarly to what is done in planar technolgies. To this purpose, gate-induced-drain-leakage (GIDL) occurring at the source-line and bit-line sides is exploited to inject a hole current towards the center of the string, thus raising its potential and triggering the emission of electrons from or the injection of holes into the storage layer.
On the other hand, NOR Flash arrays target code storage applications, therefore fast random access operation at the byte level and strong raw array reliability represent two mandatory requirements to be met. For this reason, differently from NAND Flash, the minimum feature size of NOR Flash technology has never been scaled beyond the 40 nm technology node. Despite this, in the last few years NOR Flash memory arrays attracted renewed interest for the implementation of hardware neural networks, which represent a promising solution to outclass (in terms of speed, power efficiency and integration density) conventional CMOS systems based on the Von-Neumann architecture in problems dealing with unstructured data, such as image recognition and classification. Hardware neural networks are computing systems, inspired to biological neural networks, made of arrays of computational units (neurons) interacting through connections (synapses) of different strength (synaptic weight). In hardware neural networks NOR Flash memory arrays are operated as artificial synaptic arrays connecting layers of adjacent neurons; each floating-gate (FG) memory cell in the array behaves like an artificial synapse receiving a voltage input at its control-gate and producing an excitatory post-synaptic current at its drain depending on cell threshold voltage. The threshold voltage value of the cells in the array is set during a learning phase to reproduce suitable synaptic weights, allowing the network to specialize its behaviour to perform a well defined task.
In this framework, the present thesis aims on one hand to investigate the GIDL-assisted erase operation in 3-D NAND Flash memory arrays. In particular, a compact model is developed to describe both the string dynamics and the threshold voltage transient during erase. On the other hand, a novel operational scheme allowing to employ mainstream NOR Flash memory arrays in neuromorphic systems is suggested, and the impact of typical Flash memory cells reliability issues on their performance is explored in detail.