|CREMONA LUCA||Cycle: XXXIII |
Section: Computer Science and Engineering
Tutor: AMIGONI FRANCESCO
Advisor: FORNACIARI WILLIAM Major Research topic
:Online power monitoring, modeling and optimization for mobile computing architecturesAbstract:
With the end of Moore’s law, the Power Wall represents one of the most limiting factors to the performance increase on nowadays computing architectures.
In particular, the ever increasing energy budget constraints imposed by current IoT computing architectures motivates the continuous research for novel power-aware optimizaat both design- and run-time.
While the formers allow to optimize the structure of the computationdevice during the design stage, the latters are gaining increasing attentions due to the huge optimization opportunities that are mainloffered as a consequence of the overprovisioned resources in the
hardware platform. Such resources are offered to deliver a more flexible platform that can accommodate different use-case scenariothat eventually greatly differ to each others in terms of the required computational power.
However, such overprovisioned resources can go underutilized in several real scenarios with a non-negligible energy waste, thus motivating the continuous research in the run-time power-aware optimization. In particular, the trend in the run-time power-aware
optimization focuses on software-based policies that leverage the available hardware mechanisms to implement the control loop, thus highlighting two different drawbacks.
First, the solely use of the available monitors and knobs prevents optimal solutions in terms of the considered quality metrics as well as the induced overheads. We note that the optimization policies are software implemented and totally decoupled from the hardware platform.
Second, the computational platform, in general, is not designed to offer efficient monitoring system of the non-functional metrics, e.g., power, temperature.
To this extent, the proposed PhD research is made of three stages and proposes a fresh view on the design of the run-time power-aware optimization policies encompassing both the hardware and the software layers.
Parts one and two aims to enhance the current platform design methodologies to deliver a sound online power monitoring system. Part three focuses on the design of run-time power-aware optimization policies that fully exploit the novel power monitoring system of the platform.
I) Power model identification
The state of the art about power model identification can be categorized in two different classes: direct and indirect power models.
Direct approaches are based on the use of analog sensors that measure the power consumption of the processor. Although they can
reach a very high accuracy, they present some drawbacks, one of them is that in this way we can only measures the overall chip power
consumption. Indirect approaches can be classified in two categories:
¿ Power Monitoring Counter solutions
¿ RTL-Based solutions
Power Monitoring Counter solutions :
This kind of solution uses some architectural information, provided by hardware counters, as predictor of a software-based power model that
is continuously updated to deliver the required run-time power estimates. Traditionally the hardware counters used for this scope are
performance counters, as they are already implemented in many computing architectures.
Although this solution results flexible and it’s applicable after the device delivery, it has some drawbacks: first of all it can be applied only to
architectures that implements such kind of hardware counters and they are supposed to be fully informative; secondly the information provided
by performance counters are difficult to extract and the reading of such information introduces a possibly large performance and power overhead.
RTL-based solutions :
Differently from the first solution, here architectural information are obtained directly from the architecture RTL design. Data are collected
by measuring the switching activity of design input and output pins and then passed to a software routines that build a power model based on
these architectural statistics and computes the power estimations. Also in this approach, the main drawbacks is due to the software
computation of power models, that introduce possible high power and performance overheads.
II) Power model implementation at RTL
One of the main novelties of this proposal is the direct RTL implementation of the power model infrastructure. After the application
of a RTL-based solution power model identification, we implement the identified model inside the architecture design, using hardware
counters and multipliers, to collect statistics from input and output signals and multiply those statistics with identified coefficients.
This ensure a zero performance overhead, since the power estimation computations are performed by separate components of the architecture.
III) Power-aware optimizations at HW/SW level
This kind of approach helps designer in better optimize the architecture, since they can easily explore different design space
exploration directions, and improve the architecture performance keeping the power consumption under control.
Furthermore, with this new methodology, we are able to provide power estimation at a higher frequency with respect to the state of the art.
Such feature enables a more fine-grained resource allocation performed or DVFS mechanism application at software level.
The research outcome is twofold.
First, a novel hardware design framework to automatically identify the power model and to implement the corresponding online power
monitoring infrastructure starting from the RTL description of the target platform. The proposed methodology methodology will be validated
against a set of sound RTL designs ranging from microcontroller-based Systems-on-Chip (SoCs) up to GPU-like multicore accelerators.
Second, a novel methodology to design run-time power-aware policies is presented. This contribution demonstrates the possibility of reducing
the power and the performance overheads of a run-time power-aware policy by leveraging the power monitoring platform offered by the
platform. Moreover, the hardware/software co-design also enusures a better, system-wide responsiveness.
 R. Rodrigues, A. Annamalai, I. Koren, and S. Kundu, “A study on the useof performance
counters to estimate power in microprocessors,” IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 60, no. 12, pp. 882–886, Dec 2013.
 A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring Mohamad
Najem, Student Member, IEEE, Pascal Benoit,Member, IEEE, Mohamad El Ahmad, Gilles
Sassatelli, Member IEEE and Lionel Torres, Member IEEE. IEEE Transactions on Computer
Aided Design of Integrated Circuits and Systems, Vol. 36, No. 7, JULY 2017