|IZZO NICCOLO'||Cycle: XXXIV |
Section: Computer Science and Engineering
Tutor: PRADELLA MATTEO
Advisor: BREVEGLIERI LUCA ODDONE Major Research topic
:Global Protection for Transient AttacksAbstract:
Computer security threats have a strong bond with information permanence, which defines the state of a device. The attacks based on the persistence of information in a computing device are generically called transient. A secure device must store its state in a multitude of functionalities that have to be resilient to such known and future attacks. In the near future, the current DRAM-based main memories will be gradually replaced by Emerging Memories such as 3D XPoint, ReRAM, STT-RAM or Memristor, which are faster, more scalable and efficient, although their non-volatility is yet another potentially vulnerable state. A secure non-volatile storage architecture will thus have to employ well-known cryptographic building blocks to guarantee strong security properties on the stored data, such as confidentiality, integrity and authenticity, even when the device is turned off. Those future architectures will have to comply with the stringent requirements of the mobile systems in terms of both performance and energy consumption. A threat that stems from the same attack model is represented by the so-called side-channel attacks. In fact, even the most efficient encryption architecture is rendered useless if a secret, e.g., a cryptographic key, is exposed through side-channel leakage, like power consumption, EM emission, and others. To protect a computing device from these attack types, first a detailed micro-architectural model of the processing units has to be derived, then the instruction scheduling of the device firmware should be modified to implement side-channel countermeasures, e.g., masking, in a secure way. On one side, the automatic inference of a micro-architectural model could lead to the deployment of portable yet efficient side-channel countermeasures, to be built into a compiler toolchain. On the other side, it will enable the creation of a leakage simulator, which could help to validate existing software countermeasures as well as to speed up the development of more efficient ones.