Motivation and State of the Art
Modern mm-Wave systems used both for radars in driver-assistance systems and for high data-rate communications will require modulation bandwidth ranging from 500MHz to about 1GHz. Analog-to-digital converters will therefore be needed with sample rate more than 1GS/s. Today's State-of-the-Art solution is based on flash, Time-Interleaved Successive-Approximation (TI-SAR), pipeline or hybrid SAR-pipeline converters. Unfortunately, the flash ADCs entail large power and area consumption, while TI-SAR and pipeline designers face the challenge of implementing a proper calibration technique to avoid degradation of SFDR.
VCO-based ADCs have been so far mainly explored in the context of low sampling rate (order of hundreds of kS/s), with the goal of achieving lower power consumption and area occupation. The basic implementation is shown in : the analog input is applied to the tuning port of a ring oscillator, whose output phases are fed to one or more counters.
The counters are periodically reset by the sampling clock, making their output word the digital code representing the input. The concept is somehow similar to the single-slope (integrating) ADC, but in a digital fashion.
The integrating action of the VCO, when moving from voltage to phase domain, allows to better exploit the structure, leveraging the ease of digital differentiation of the sampled phases by means of XOR gates to obtain open loop first order noise shaping .
phases can be sampled by means of D-type Flip-Flops, quantizing the information right after the integration. Each register stores then one out of 2N
possible states of the oscillator. The comparison between successive states can be easily performed by XOR gates, the sum of whose outputs represents the number of transitions occurred in the time elapsed between samples. The overall chain results in an analog-domain integration due to voltage-to-phase conversion, time and amplitude quantization by sampling, and digital-domain differentiation. The signal transfer in the frequency domain is then unitary, whereas the quantization noise only experiences differentiation, resulting in first order shaping.
The main advantages are that the VCO intrinsic integration of the time information allows indeed to avoid the area/power of the Op-Amp needed in the mainstream voltage-domain switched-capacitor integrator. On top of this, VCO-based ADCs are believed to better benefit from technology scaling, given the highly digital nature of the converter. On the other hand, a critical issue of VCO-based ADCs is their higher sensitivity to voltage supply disturbances (mainly induced by the VCO) and the nonlinearity of the VCO itself.
As a matter of fact, a recent work by Baert  appeared at ISSCC 2019 presenting a 7-fold reduction of power consumption and area occupation with respect to conventional approaches. Ref.  makes use of time-interleaving to reduce the operating frequency of each path, allowing LUT-based calibration. Even more recently, advanced non-uniform sampling (NUS) techniques applied to a VCO-based ADC were presented by Chen , confirming the advantage in terms of power consumption, even accounting for the calibration.
Even looking at the common metrics used to quantitatively assess the performance of the converter, we can conclude that VCO-based ADCs at GS/s rates outperform conventional SAR or pipeline ADCs.Goals
In this research, we intend to:
Project impact and relevance
- Compare the theoretical performances of VCO-based ADC versus a SAR-based ADC in the GS/s range;
- Understand the ultimate limits of GS/s converters and estimate the impact of nonidealities, extending the work in ;
- Implement a GS/s, 10 ENOB, 800MHz signal bandwidth, open-loop TI VCO-based ADC, tackling the VCO nonlinearity and supply sensitivity by means of suitable digital calibrations;
- Design of an automatic digital pre-distortion scheme to mitigate the VCO nonlinearity issue, that can be either adaptively compensated for by using a replica VCO as in , or background calibrated, embedding the VCO in a PLL, with a proper bandwidth expansion technique;
- Tackle the impact of VCO supply sensitivity, using either differential signalling with two VCOs, or exploring the idea of supply noise cancellation;
- Address the issues of time interleaving by means of digital calibrations. This study will also be useful for other types of time-interleaved converters, as for instance SAR ADCs.
From an academic point of view, we believe that VCO-based ADCs at GS/s are still a new and thriving field of research. This is because they have been so far mostly explored at lower sample rates. The extension of this approach to much higher bit rates seems promising, as the first implementation at GS/s rate shows some relevant advantages in terms of power and area with respect to other approaches . The impact of supply sensitivity on the ultimate limit of VCO-based ADC, and contribution of power and area of supply regulators to mitigate such sensitivity have not been yet discussed or addressed in open literature. We should also consider that unlike kS/s VCO-based ADCs, in ADCs at GS/s rate, the extra power consumption of a voltage regulator does not dominate the overall power consumption. The evaluation of the relative contribution of voltage regulators to the total power consumption is another interesting topic to be addressed. References
 M. H. Perrot, 2007. [Online]. Available: www.cppsim.com.
 D. W. P. A. U. Wismar, "A 0.2V, 7.5 W, 20 kHz modulator with 69 dB SNR in 90 nm CMOS," in ESSCIRC
 M. B. a. W. Dehaene, "A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step," in IEEE International Solid- State Circuits Conference - (ISSCC)
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 T. W. a. M. S. Chen, "A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing," IEEE Journal of Solid-State Circuits,
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