|GALIMBERTI ANDREA||Cycle: XXXV |
Section: Computer Science and Engineering
Tutor: AMIGONI FRANCESCO
Advisor: FORNACIARI WILLIAM Major Research topic
:Design and implementation of secure and efficient computing platforms for the Internet of ThingsAbstract:
The Internet of Things (IoT) delivers a tightly connected world, that allows to satisfy the ever-increasing request from the users for services that are specifically tailored to their needs and that are available anywhere and anytime. Research has shown the possibility to offer highly personalized services, such as augmented reality, face recognition and voice assistants, by exploiting machine learning and artificial intelligence techniques. However, tailoring these services to users requires the exchange of an increasing amount of personal information and sensible data, creating a significant problem of privacy and security.
It is therefore paramount to design computing solutions that allow to support in an efficient way all the applications of the IoT digital world, while at the same time guaranteeing the security of the users’ data.
In this scenario, the goal of my PhD research is to explore solutions, at both the architectural and microarchitectural levels, that support the new applications of the IoT world on portable embedded systems. In particular, I aim to design an efficient general-purpose computing platform that targets both machine learning applications and security aspects ranging from post-quantum cryptography to protection from side-channel attacks. The key advantage of my research lies in the possibility of designing a hardware platform for IoT that provides a computation that is both secure and efficient at the same time.
In order to achieve this goal, the three-year PhD research has been organized in five parts: the analysis of the state of the art, tthe hardware/software codesign of accelerators for post-quantum cryptography, the hardware/software codesign of accelerators for machine-learning applications, the integration of the developed accelerators in an embedded-class computing platform that implements the RISC-V ISA, and finally the validation of the resulting platform.