|Thesis abstract: |
The ever growing market of mobile communication and digital consumer electronics has stimulated the rapid development of Flash memory technology. For more than 20 years the conventional floating-gate technology has been able to meet the requirements of higher storage density, higher programming/erasing speed, higher reliability and lower power design through a continuous scaling of the cell size. However, the floating gate technology faces nowadays difficult technical challenges and some physical limitations towards further scaling. The charge-trap memory cell is considered today the most practical evolution of the floating-gate Flash cell, allowing improved reliability and scaling perspectives. However, the discrete nature of the stored charge necessarily gives rise to statistical issues related to the number and position fluctuation of the electrons in the storage-layer, determining a statistical dispersion of the threshold voltage shift after the program operation. This statistical dispersion is expected to be further worsened when considering the additional contribution of atomistic doping to non-uniform substrate inversion, enhancing percolative source-to-drain conduction. Moreover the statistical nature of the process ruling the injection of charge from the substrate into the storage layer, may represent a further important variability source for the program operation of nanoscale charge-trap memory devices, compromising the tightness of the programmed threshold-voltage distribution, as already pointed out for floating-gate devices. Cell scaling increases the impact of these variability sources, as the number of charges (electrons and ionized dopants) decreases shrinking the cell dimensions. This thesis focuses the attention on the statistical variability affecting the reading and programming operations of nanoscale charge-trap memories. Chapter 1 briefly introduces the floating-gate Flash technology, pointing out the main scaling limits for both NAND and NOR architectures. Then the charge-trap technology is presented highlighting its potential benefits in terms of reliability, scaling perspective and technological feasibility. The end of the chapter is devoted to present the major sources of statistical variability for the charge-trap technology. Chapter 2 gives a thorough overview of the issues related to the resolution of individual discrete charges in 3D drift-diffusion simulations. Chapter 3 presents a comprehensive investigation of threshold voltage shift variability in deeply-scaled charge-trap memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. The scaling trends and the practical impact of these statistical effects on cell operation are also analyzed. Chapter 4 addresses the study of charge-trap memory programming variability, presenting a physics-based Monte-Carlo model developed to simulate the statistical electron injection process from the substrate to the storage layer. Chapter 5 presents a channel doping engineering study aimed to the random telegraph noise (RTN) suppression in nanoscale Flash memories. The conclusions of the thesis will be summarized at the end of the manuscript, outlining what has been accomplished and proposing some future work that can extend and improve the understanding of the effects of variability on the charge-trap memory performances.