|Thesis abstract: |
Scaling of the floating-gate Flash technology is more and more severely constrained by physical limitations such as parasitic cell-to-cell interference and leakage currents from the charge storage layer. A promising alternative is offered by charge-trap (CT) cells, such as SONOS and TANOS, solving many of the constraints of the floating-gate technology while preserving its structural simplicity and process compatibility. However, the feasibility of a high-density non-volatile memory technology based on CT storage has not been clearly demonstrated so far. Aim of the thesis is to investigate the performance and limitations of CT storage for future non-volatile technologies. Experimental and modeling efforts are devoted to the understanding of the basic-physics and dynamics ruling charge storage in CT layers, mainly focusing on silicon nitride devices. With experimental measurements and modeling efforts, charge trapping/detrapping in the CT layer is investigated and modeled in detail, analysing the achievable performance and limitations on both planar and cylindrical devices and developing simulation tools to predict the functionality of high-density memory arrays.