|Thesis abstract: |
This work has been focused on the study, design and test of an innovative spectroscopic-grade Front-End ASIC for semiconductor radiation detectors in space applications. The most crucial requirement is that the ASIC must be able to process input charge signals from 25 k to 100 M electrons, thus employing an input dynamic range consisting of more than three orders of magnitude (1:4000). Other ASIC requirements are a low readout noise (ENC < 3 kelectrons r.m.s.), a low power consumption (< 5 mW/channel) and the possibility to work with very high detector capacitances up to 300 pF.
Literature presents several solutions for handling signals belonging to very wide dynamic ranges, like the Time to Charge Conversion (CTC) and Time Over Threshold (TOT) techniques, but they are not suitable for our purpose, mainly because they imply power consumptions that are too high (tens or hundreds of mW/channel, typically). In addition, these techniques also require the presence, on-chip, of digital circuits that continuously operate very close to the analog path, which can result in parasitic cross-talks that can seriously degrade the system analog performances, especially in terms of readout noise and disturbances.
The aim of this work has thus been to propose, study and test an innovative ASIC performing an automatic real-time auto-ranging operation. The technique is based on the subdivision of the overall input dynamic range into smaller sub-ranges, each one covering a single decade. When a charge pulse is received from the detector, the system recognizes the sub-range it belongs to and selects, in real-time, the gain of the channel such that the signals of each sub-range can use the whole output swing of the circuit, which is thus the same for all the sub-ranges.
In order to implement such operation, the ASIC must necessarily work in time-variant regime and so a first step consisted in a theoretical study aimed to verify its ability to properly work without degrading the noise performances.
In a second phase the circuit has been designed and simulated and the good simulation results allowed us to pursue with the third step, which consisted in the realization of two ASIC prototypes: the first one containing only the channel analog section and the second containing the entire circuit.
Both these prototypes have been experimentally characterized, providing good and promising results. The measurements also pointed out some unexpected problems, which have been analyzed and solved in a fourth step, that has led us to the design of a new ASIC prototype.