|Thesis abstract: |
The research target is to demonstrate the feasibility of an efficient wideband phase modulator to be used in radio transmitters for high-data-rate 4G communication standards (such as WiMAX) in low-cost CMOS processes.
The investigated architecture is based on a digital Phase Locked Loop (PLL) and a two-point injection scheme. At high bit rates, this modulator requires a controlled oscillator with wide tuning range and becomes critically sensitive to the gain and delay spread between the two injection paths, considerably degrading the achievable error-vector magnitude (EVM) and causing significant spectral regrowth.
These issues are overcome thanks to an innovative topology of the digital PLL, the use of a single bit phase detector in place of a power hungry time to digital converter (TDC) and the implementation of an automatic background regulation of the gain and delay mismatches of the two injected paths.
The test chip is designed and fully integrated in 65nm CMOS and the measurements achieve EVM lower than 36dB at 4GHz for both a 20Mb/s QPSK and 10Mb/s GMSK modulation and ACPR lower than -53dB for a GMSK signal.