|Thesis abstract: |
The work presented here has been made within a scientific collaboration between Politecnico di Milano, University of Pavia, INFN-Trieste, INFN-IASF Bologna and INAF-IASF Rome, related to the assessment phase of LOFT mission. The LOFT mission (Large Observatory For X-ray Timing) is one of the four cosmic missions selected by European Space Agency (ESA) as a medium class space mission for high resolution X-ray observation of the compact objects and ultra-dense matters in the space. Within the collaboration, the task of Politecnico di Milano is the design and experimental characterization of the Front-End Electronic (FEE) circuit, named VEGA, for the readout ASIC of LOFT Large Area Detector. This doctoral thesis is focused on the design, simulation and experimental characterization of the first prototype of VEGA: a low-noise, low-power Front-End Electronic (FEE) circuit for high resolution X-ray spectroscopy and imaging with the input photon energy range from 500 eV to 60 keV. The VEGA FEE is specifically optimized to readout signals from a large area monolithic Silicon Drift Detectors (SDDs) with an active area of about 76 cm2, the anode capacitance of about 350 fF and the anode leakage current from 0.7 pA to 10 pA (the LOFT LAD). The VEGA circuit is comprised by an analog, a mixed-signal and a logic circuit to accomplish all the required functionalities for high resolution X-ray spectroscopy as required by the LOFT mission. The analog chain includes a charge sensitive preamplifier followed by a first order semi-Gaussian shaper and a peak stretcher/sample and hold circuit. The mixed-signal section includes an amplitude and a peak discriminator circuits. The compact logic circuit is implemented in order to control the functionalities of the analog and the mixed-signal sections. Various functionalities are implemented in the VEGA ASIC including: 3-bit digitally selectable shaping time, 4-bit digitally selectable fine threshold, pile-up rejection, preamplifier disabling and discriminators disabling. The FEE circuit is designed and tested in single channel and 32 channels versions. The designed ADC-ready FEE circuit opens a new state of the art in the design of a low-noise, low-power FEEs for large area detectors application. The main characteristics of the VEGA ASIC can be summarized as: 1. Compact size: 200 µm × 500 µm, suitable for implementation with multi-anode Drift Detector. 2. Very low-noise: intrinsic ENC of about 12 electrons r.m.s. at 3.6 µs shaping time, equivalent to 104 eV FWHM on pulser line; this value is comparable with the lowest noise FEE ever designed 3. Very low-power consumption: 420 µW per channel, which is a factor of 4 lower than the lowest power consumption FEE for X-ray Drift Detectors ever published.