|Thesis abstract: |
Academic and industrial research in the field of high-speed Nyquist-rate Digital-to-Analog Converters (DACs) is pushed forward today by the growing interest in multi-carrier multi-band transmitters, for both wireless and wireline systems. In particular, several communications standards have been recently developed requiring a DAC in the transmitter path with a sampling frequency in the GS/s range, while posing, at the same time, extremely stringent constraints on resolution, linearity and power.
In this framework, essential objective of the research activity has been the definition and the development of new design methodologies and techniques for the realization of high-speed high-performance DACs suitable for the integration in ultra-scaled CMOS technologies, which allow overcoming the fundamental trade-offs limiting performances. In particular, a new digital technique for the linearization of DAC static characteristic has been introduced, which is based on the extensive use of digital LMS adaptive filtering. As static non-linearity due to analog circuits impairments is canceled out in digital domain, a design full-oriented at optimizing high-frequency performances is allowed. Furthermore, the digital style of the proposed method particularly benefits from technology scaling in terms of area and power consumption.
To demonstrate its effectiveness, the proposed technique has been applied to the design of a 10-bit 2.5-GS/s current-steering DAC in 28-nm CMOS, to be integrated in the baseband section of a 60-GHz transmitter. Simulation results show a linearity improvement ranging from 26dB at DC to 15dB at the highest input frequency, leading to a DAC SFDR greater than 65dB across the entire Nyquist bandwidth.