|Thesis abstract: |
While the aggressive technology scaling is fueling the integration of more and more transistors in a single die, power, heat and reliability constraints forced the computer industry to shift from single-core to multi-core architectures in order to better manage such constraints. In this scenario, the need for huge and flexible interconnection resources highlights the limits of classic bus-based architectures and Networks-on-Chip (NoCs), also called On-Chip Networks (OCNs), emerged as a viable solution to deliver such requirements. Most of the previous research focused on NoC optimizations exploiting actuators such as DVFS and power gating, eventually combined with novel microarchitectural solutions without carefully consider the associated overheads which can partially or even totally shadow the benefits of the proposed methodology. Moreover, the need to account for both cores and memory subsystem interactions during the NoC design and optimization, requires flows providing a variety of accurate estimates related to the considered architecture. In this perspective, the proposed research provides contributions in three different ways to explore and optimize the power-reliability-performance figure of merit in NoC-based multi-cores. First, a complete cycle accurate simulation framework which allows to collect power, performance and reliability metrics on both cores and NoC has been developed starting from available open source tools. Some of them have been enhanced while part of the toolchain has been developed from scratch. Second, two different actuators, i.e. power gating and DFS with partial support for voltage scaling, have been integrated in the simulation flow starting from accurate analytical models. Furthermore, the developed SPICE models allowed to integrate both their timing and power consumption. The proposed actuators have been coupled with the NoC model enabling the possibility to use them on a per router basis up to islands of routers of different sizes. The third contribution is related to the development of three different methodologies jointly considering power, reliability andperformance. In particular, the first proposal focuses on the dynamic-power/performance trade-off in NoC routers exploiting the DFS model by implementing a control-based methodology. The second proposal concerns static-power/performance optimization of routers' buffers, which is the main static power source. It effectively exploits the power gating support offered by the implemented simulation flow. Moreover, the proposal takes into account the NBTI aging mechanism, that is a physical phenomena which tends to degrade the CMOS logic performance over the time. The last methodology focuses on static operating frequency assignment in a multi-core to reduce the power consumption, with the final objective to control the thermal profile. A complete linear model of the system has been created to optimally set the frequencies considering several figures of merit. The research ideas still in a early stage of maturity, representing the directions of the future investigations, have been gathered in the Appendix. Such chapter is split in two parts. First of all it is proposed a methodology which combines multiple mechanisms i.e. DFS and adaptive routing, to aggressively face with power-performance trade-off. It is worth to note that the adaptive routing represents an additional mechanism to manage the already considered metrics. Second, a preliminary DVFS timing and power models have been integrated in the NoC model, enabling the simulation analysis to compares DVFS, DFS and the static frequency solutions.