|TESOLIN FRANCESCO||Cycle: XXXV|
Advisor: LEVANTINO SALVATORE
Tutor: SOTTOCORNOLA SPINELLI ALESSANDRO
Major Research topic:
Design of a multi-core digital PLL array for ultra-low jitter phased-arrays applications
Applications such as 5G New-Radio (NR) and radar for autonomous drive, requires either an ultra-low jitter frequency synthesizer and phased-array antennas that needs to be driven by high-accuracy phase-shifters. The aim of the major Ph.D. project is to build beyond-state-of-the-art frequency synthesizer in scaled CMOS technology, with spectral purity performances and phase-shifting capabilities which are suitable for the above-mentioned applications. The key idea, in fact, is to realize a local oscillators (LOs) arrays which directly feed each of the phased-array element, providing internally in each of the LO the required phase-shift. Furthermore, the adoption of multiples LOs causes an improvement on the system phase noise (PN) performances which is proportional to 10log10(N), where N is the number of LOs adopted.
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