Current students


Section: Electronics

Major Research topic:
Digital algorithms enabling 5G frequency synthesis in 28nm CMOS

5G local oscillators for wireless transceivers must satisfy stringent requirements regarding their rms integrated jitter, frequency resolution, spectral purity, frequency switching time and robustness to PVT variations. At the same time multiple functionalities like ultra low-EVM frequency modulation, relative phase shifting and presence of I/Q channels with ultra-small I/Q unbalance must be ensured.
To ensure a small footprint of the system and compatibility with other key building blocks it is also required that the solution is fully integrable in scaled CMOS technologies, where analog behaviour of MOS transistors is strongly affected by short-channel effects, PVT variations and mismatches, causing additional issues in the practical implementation. The larger target frequencies (60-100 GHz) with respect to previous standards exacerbate these problems since mismatches, noise and parassitics dramatically worsen the performances of LC oscillators in mmW-band.
Moreover the large number of the overall system parameters may prohibitively increase the time-to-market and equivalent cost-per-die, due to inevitable post-tapeout calibrations, that however do not avoid parameter drifts due to temperature and environmental changes. 
A possible solution to these problems may rely on the use of digital algorithms operating in the background of the main system, calibrating its parameters in order to simultaneously achieve the optimal setting and desynthetize the performances from analog behaviours by possibly correct for non-idealities induced by analog components.
The implementation of articulated algorithms in a fully analog fashion is tipically prohibitive in terms of area, power dissipation and design complexity, while it is straightforward in the digital domain since it is carried out writing HDL codes and following standard RTL to layout digital flow thus avoiding long design iterations typical of manual analog design. Small footprint is instead ensured by the scaling of CMOS technology.
For these reasons digital PLLs are attractive solutions to perform agile and small-footprint local oscillators, however they suffer from problems intrinsically connected to to the usage of quantization operations inside their loop and the presence of 2 inevitable analog blocks, namely a digitally-controlled-oscillator (DCO) and a Digital-to-time converter (DTC), which non-linearity severely affects their overall performances, both in terms of rms integrated jitter, SFDR and locking time. The aim of this work is to show that, by properly designing digital corrections and algorithms, the performance gap between digital and analog PLLs can be bridged.