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Functional verification of mixed-signal designs is typically performed by splitting the analog parts of the circuit from the digital ones, and interconnecting the latter with a data-flow model of the former. This approach provides both the capability to analyze time latency between signals, and real-values precision for the signals values representation. This design approach can be very effective in early development phases, but it is not very effective when the prototyping phase is reached. In fact, given the nature of HW emulators, it is not possible to emulate the analog part of the design together with the digital part without significantly remodeling it. Furthermore, with such a verification methodology it is not possible to consistently reuse previously designed verification steps for different designs. This research work explores alternative methodologies for mixed-signal verification which goals are to interface with existing verification environments through the high-level synthesis of high-level design descriptions.