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SCALETTI LORENZOCycle: XXXVI

Section: Electronics
Advisor: BERTULESSI LUCA
Tutor: SOTTOCORNOLA SPINELLI ALESSANDRO

Major Research topic:
Clock generation systems and timing circuits for high-resolution wide-band ADCs

Abstract:
The constant evolution of CMOS technology, every year faster and shrinking in size, is expected to continue in the next future, bringing new devices in everyone’s life exponentially increasing the amount of data electronically transmitted. The so-called "Internet of Things" (IoT) refers to the trend of integration of connected devices in everyday appliances, with applications covering home automation and smart cars, wearable devices and even Industry 4.0 and smart cities. IoT will greatly increase the number of connected devices, many of which will be very small, battery-operated embedded systems, that require low power during operation. In this framework wireless networks will play a very important role, starting from the next generation of mobile networks called 5G, which is in current development and promises increased data rates with lower latency and power consumption. The goals are achieved exploiting high-GHz (mmWave) frequency bands, previously deemed not suitable for commercial operation, such as 28, 38, 64 and 71GHz, which require smaller antennas and allow for larger continuous RF bandwidths which in turn enable higher data rates. In this framework, high-frequency and high-resolution data converters are needed, to properly interface computing devices and wireless transceivers.
State-of-the-Art ADCs achieving high conversion-rates with high accuracy are often based on pipelining, time-interleaving, or a combination of both. Architectures like SAR converters are also widely adopted for their power efficiency, although they can not reach very high conversion rates without the aforementioned techniques. Since they deal with high-frequency signals, this type of converters need very accurate timing to ensure the required accuracy of the sampled inputs. In fact, the impact of timing errors on the achievable SNDR (Signal to Noise and Distortion Ratio) at the output of the converter depends on the input signal properties, in particular on its frequency, which is an indication of the "speed of variation" of the signal. For example, a 500MHz signal needs to be sampled with a random timing error (usually called "jitter") lower than 255fs in order to obtain 10 equivalent bits at the output of the converter, and the maximum allowable jitter halves for every additional bit. Moreover, architectures such as time-interleaved converters need multiple clock phase which, additionally, need to be accurately synchronized one to each other.
The goal of this research is to study clock generation systems for data converters with such stringent requirements, focusing both on the specifications and implementation of the analog building blocks and on the opportunities that digital correction algorithms can offer.