CARLONI FILIPPO | Cycle: XXXVII |
Section: Computer Science and Engineering
Advisor: SANTAMBROGIO MARCO DOMENICO
Tutor: MARTINENGHI DAVIDE
Major Research topic:
An advanced HW/SW framework for efficient Regular Expression execution
Abstract:
Finite State Machines (FSMs), or the most common and equivalent Regular Expressions (REs) representation, find relevant usage in applicative scenarios such as computer security or genomics/proteomics. Examples are finding an intrusion in a system or developing specific health and drug treatments based on the patient's genome. However, such applications require colossal data analysis, resulting in long computational times and high energy consumption.
Specifically, current solutions miss the point due to unbalancing between the domain's flexibility and execution efficiency, creating two macro areas.
The first area comprises the software solution executed on CPUs. They generalize the REs execution supporting almost all types of REs operators in every context, but they miss specific applications' stringent execution times and energy efficiency requirements.
Instead, the hardware accelerators area comprises tuned solutions for a reduced REs operators subset and pre-fixed working conditions, but they provide excellent execution times and high energy efficiency.
Instead, based on the idea of REs as a programming language, this research project proposes a full-stack Hardware/Software (HW/SW) framework for efficient REs execution to fill the existing gap. The framework will comprise a runtime reconfigurable multicore Domain-Specific Architecture (DSA), a smart compiler, and a runtime manager, optimized individually for REs execution.
The novelty resides in the combination of SW flexibility with HW specialization to create a solution able to overcome the limitations of the existing ones, boosting performance and energy efficiency.
This research project aims to improve REs execution drastically and to pave the way for future HW/SW domain-specific accelerators.
Specifically, current solutions miss the point due to unbalancing between the domain's flexibility and execution efficiency, creating two macro areas.
The first area comprises the software solution executed on CPUs. They generalize the REs execution supporting almost all types of REs operators in every context, but they miss specific applications' stringent execution times and energy efficiency requirements.
Instead, the hardware accelerators area comprises tuned solutions for a reduced REs operators subset and pre-fixed working conditions, but they provide excellent execution times and high energy efficiency.
Instead, based on the idea of REs as a programming language, this research project proposes a full-stack Hardware/Software (HW/SW) framework for efficient REs execution to fill the existing gap. The framework will comprise a runtime reconfigurable multicore Domain-Specific Architecture (DSA), a smart compiler, and a runtime manager, optimized individually for REs execution.
The novelty resides in the combination of SW flexibility with HW specialization to create a solution able to overcome the limitations of the existing ones, boosting performance and energy efficiency.
This research project aims to improve REs execution drastically and to pave the way for future HW/SW domain-specific accelerators.
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