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Technology scaling enables the integration of more transistors, reducing area occupation and cost and increasing the performance compared to previous generations. Modern electronic systems tend to move most signal processing in the digital domain. Consequently, analog-to-digital converters (ADCs) play a fundamental role in determining the overall system performance.

One of the most critical applications of ADCs is in wireless transceivers, where the requirements set by the latest mobile standards pose significant challenges. The high channel bandwidth implies sampling rates in the GS/s range, while high-order modulation schemes demand 12-bit resolution quantizers [1].
To overcome the speed limitation of single-core ADCs without reducing the resolution, time-interleaved (TI) ADCs have been introduced [2]. Time-interleaving consists of parallelizing M channels, where the overall sampling rate is increased to M times the sampling rate of the single ADC without significantly degrading the energy efficiency.

Despite the power vs. speed trade-off advantage of TI-ADCs over single-channel converters, the resolution is intrinsically limited by the differences in the transfer characteristic among the slices. Offset, gain, timing skew, and bandwidth mismatches result in spurious tones and replicas of the input signal [3], which degrade the signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The latter is especially critical in wireless systems, where weak signals often need to be detected with adjacent channels or large blockers.

A digital-assistance approach is more frequently employed to calibrate interleaving mismatches and reduce the resolution gap between standalone converters and TI-ADCs [4]. Digital assistance allows exploiting technology scaling by relaxing the specifications of analog circuits and letting digital algorithms compensate for conversion errors. Recent works report promising results over single-channel converters by leveraging time-interleaving, adaptive calibration algorithms, and scaling-friendly and hybrid architectures.

ADCs with an effective number of bits (ENOB) beyond 10.5 and a sampling rate of more than 1GS/s, relevant for the next-generation mobile applications, comprise only a few designs in the literature. Most of them are pipelined ADCs with a power consumption much higher than 1W [5, 6].

The research project aims to investigate ADCs compatible with the stringent requirements of the next-generation mobile applications and implement the proposed architecture in a 28nm CMOS technology. Time-interleaving and extensive use of digital calibrations will be investigated, along with an energy-efficient channel design.

Scaled technologies present challenges in analog design. The strategy is to merge process advantages—such as the reduced cost of digital logic—with smart architectural and circuit choices to outperform state-of-the-art ADCs, both in energy efficiency and raw performance. A time-interleaved SAR-based ADC will be designed to achieve sampling rates belonging to the pipelined domain but at lower power consumption, thanks to the absence of analog amplifiers. Core and interleaving calibrations will be investigated to reach more than 10.5 ENOB beyond 1 GS/s.

REFERENCES
[1] Y. Huo, X. Dong, and W. Xu, "5G Cellular User Equipment: From Theory to Practical Hardware Design," in IEEE Access, vol. 5, pp. 13992-14010, 2017

[2] W. C. Black and D. A. Hodges, "Time interleaved converter arrays," in IEEE Journal of Solid-State Circuits, vol. 15, no. 6, pp. 1022-1029, Dec. 1980

[3] B. Razavi, "Design Considerations for Interleaved ADCs," in IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1806-1817, Aug. 2013

[4] B. Murmann, "Digitally assisted data converter design," 2013 Proceedings of the ESSCIRC (ESSCIRC), 2013, pp. 24-31

[5] A. M. A. Ali et al., "A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration," in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2857-2867, Dec. 2014[6] H. Shibata, V. Kozlov, Z. Ji, A. Ganesan, H. Zhu, and D. Paterson, "16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving −161dBFS/Hz NSD," 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 278-279