Current students


Section: Electronics

Major Research topic:
Architecture- and circuit-level innovations of high-speed time- interleaved analog-to-digital converters

Analog-to-digital converters (ADCs) featuring high-speed, medium resolution and low power consumption are needed in wireless communication systems such as sixth generation (6G) receivers, radar and instrumentation. The time-interleaved (TI) architecture satisfies the requirements of these applications.
Pipeline and successive-approximation-register (SAR) ADCs are typically used as channels of TI ADCs with GS/s sampling rates. The pipeline architecture is faster than a SAR one, because the conversion is divided in a cascade of stages. It requires, however, the presence of highly linear amplifiers. Short-channel effects and small voltage headrooms limit the linearity of such amplifiers in deep-scaled CMOS technologies. Moreover, they feature a large power consumption to satisfy the noise constraints of medium resolution ADCs. Avoiding altogether residue amplification employing SAR cores removes the challenge of designing a high-linear amplifier. The main advantage of the SAR architecture is that it is scaling friendly, since it is based mostly on digital circuitry. Thus, it dissipates a smaller power consumption than pipeline ADCs. However, DAC settling and comparator speed ultimately limit the speed of this architecture. Therefore, there are two main approaches in designing high-speed TI ADCs. One is to interleave typically eight or less high-speed pipeline sub-ADCs and the other one is to use a large number ­of low-power SAR ADCs, e.g., 16 channels or even more. Extensive calibration in the digital domain helps to cope with channel mismatches and amplifiers non-idealities achieving a signal-to-noise- and-distortion ratio (SNDR) close to 62 dB (10-bit resolution) with an input bandwidth of multiple GHz. On the one hand, a large number of low-power SAR ADCs increases calibration complexity and makes the input switched-impedance difficult to drive. On the other hand, using a small number of pipeline sub-ADCs is easier to drive and calibrate, but it requires a large power consumption. A promising solution to breake this trade-off is a TI ADC with a pipeline-SAR sub-ADCs. This kind of architecture recently showed good performance in literature. The Schreier Figure of Merit (FoM, defined as the sum of the SNDR and the ratio between bandwidth normalized to the power consumption in logarithmic scale) of recently published works is in the range 145 dB - 165 dB range.

The aim of this research project is to propose a high-speed TI ADC in a 28-nm CMOS technology satisfying the requirements of the 6G standard communication with a Schreier FoM larger than 160 dB. In particular, the ADC will be designed to have an SNDR larger than 62 dB and a large input bandwidth (> 1 GHz).